The present invention relates in general to a process for the fabrication of semiconductor components. More particularly, the invention relates to a process in which the semiconductor components are fabricated with a controlled spacing of etched channels. The process of the present invention is in particular utilized in fabricating a monolithic array of elements such as a PIN diode array.
In connection with the description of the process of this invention and the related prior art processes, reference is made to microwave control devices such as the PIN diode. However, it is understood that the concepts of the present invention also apply to other forms of semiconductor control devices.
The aforementioned diode is known to be comprised of P-doped and N-doped regions separated by an intrinsic (undoped) region. For low RF loss and optimum on/off switching performance, the following properties are desired for such a device;
1. Well-defined and heavily doped P and N regions. PA1 2. P and N regions oriented as parallel surfaces to the I-region. PA1 3. I-regions that are well passivated with oxide where exposed to external surfaces. PA1 4. I-region dimensions well controlled and consistent.
The control and uniformity of the I-region geometry is particularly important when the PIN diodes are connected in series or parallel because variations in uniformity effect the proper RF signal distribution and DC control bias distribution.